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Freescale Semiconductor Technical Data
Document Number: MC13192 Rev. 2.9, 08/2005
MC13192/MC13193
(Scale 1:1)
MC13192/MC13193
2.4 GHz Low Power Transceiver for the IEEE(R) 802.15.4 Standard
Device MC13192 MC13193
Package Information Plastic Package Case 1311-03 (QFN-32) Ordering Information Device Marking 13192 13193 Package QFN-32 QFN-32
1
Introduction
Contents
1 2 3 4 5 6 7 8 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 3 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 3 Electrical Characteristics . . . . . . . . . . . . . . . 8 Functional Description . . . . . . . . . . . . . . . . 12 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 15 Applications Information . . . . . . . . . . . . . . . 18 Packaging Information . . . . . . . . . . . . . . . . . 23
The MC13192 and MC13193 are short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13192/MC13193 contain a complete 802.15.4 physical layer (PHY) modem designed for the IEEE(R) 802.15.4 wireless standard which supports peer-to-peer, star, and mesh networking. The MC13192 includes the 802.15.4 PHY/MAC for use with the HCS08 Family of MCUs. The MC13193 also includes the 802.15.4 PHY/MAC plus the ZigBee Protocol Stack for use with the HCS08 Family of MCUs. With the exception of the addition of the ZigBee Protocol Stack, the MC13193 functionality is the same as the MC13192. When combined with an appropriate microcontroller (MCU), the MC13192/MC13193 provide a cost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processor
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.
Features
can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBeeTM networking. For more detailed information about MC13192/MC13192 operation, refer to the MC13192/MC13193 Reference Manual, part number MC13192RM. Applications include, but are not limited to, the following: * Remote control and wire replacement in industrial systems such as wireless sensor networks * Factory automation and motor control * Energy Management (lighting, HVAC, etc.) * Asset tracking and monitoring Potential consumer applications include: * Home automation and control (lighting, thermostats, etc.) * Human interface devices (keyboard, mice, etc.) * Remote entertainment control * Wireless toys The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with 5.0 MHz channel spacing per the IEEE 802.15.4 specification. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control.
2
* * * * * *
Features
Recommended power supply range: 2.0 to 3.4 V 16 Channels 0 dBm nominal, programmable from -27 dBm to 4 dBm typical maximum output power Buffered transmit and receive data packets for simplified use with low cost MCUs Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode (compatible with IEEE Standard 802.15.4) Three power down modes for power conservation: -- < 1 A Off current -- 1 A Typical Hibernate current -- 35 A Typical Doze current (no CLKO) RX sensitivity of -92 dBm (typical) at 1.0% packet error rate Four internal timer comparators available to reduce MCU resource requirements Programmable frequency clock output for use by MCU Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration. Seven general purpose input/output (GPIO) signals
MC13192/MC13193 Technical Data, Rev. 2.9
* * * * *
2
Freescale Semiconductor
Block Diagrams
* *
Operating temperature range: -40 C to 85 C Small form factor QFN-32 Package -- RoHS compliant -- Meets moisture sensitivity level (MSL) 3 -- 260 C peak reflow temperature -- Meets lead-free requirements
3
Block Diagrams
Figure 3 shows a simplified block diagram of the MC13192/MC13193 which is an IEEE Standard 802.15.4 compatible transceiver that provides the functions required in the physical layer (PHY) specification. Figure 4 shows the basic system block diagram for the MC13192/MC13193 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements.
4
Data Transfer Modes
The MC13192/MC13193 has two data transfer modes: 1. Packet Mode -- Data is buffered in on-chip RAM 2. Streaming Mode -- Data is processed word-by-word The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary applications, packet mode can be used to conserve MCU resources.
4.1
Packet Structure
Figure 5 shows the packet structure of the MC13192/MC13193. Payloads of up to 125 bytes are supported. The MC13192/MC13193 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is calculated and appended to the end of the data.
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 3
Data Transfer Modes
4.2
Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon the baseband energy integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD), the correlator "de-spreads" the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data. The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 s period after the packet preamble and stored in RAM. If the MC13192/MC13193 is in packet mode, the data is processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt. If the MC13192/MC13193 is in streaming mode, the MCU is notified by an interrupt on a word-by-word basis. Figure 1 shows CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above IEEE 802.15.4 Standard requirements. Figure 2 shows energy detection/LQI reported level versus input power. Note that for both graphs the required IEEE 802.15.4 Standard accuracy and range limits are shown.
-50
Reported Power Level (dBm)
-60
-70
802.15.4 Accuracy and range Requirements
-80
-90
-100 -90
-80
-70 Input Pow er (dBm)
-60
-50
Figure 1. Reported Power Level versus Input Power in Clear Channel Assessment Mode
MC13192/MC13193 Technical Data, Rev. 2.9 4 Freescale Semiconductor
Data Transfer Modes
-25 Reported Power Level (dBm) -35 -45 -55 -65 -75 -85 -85 802.15.4 Accuracy and Range Requirements
-75
-65
-55
-45
-35
-25
-15
Input Pow er Level (dBm)
Figure 2. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 5
Data Transfer Modes
4.3
Transmit Path Description
For the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency. If the MC13192/MC13193 is in packet mode, data is processed as an entire packet. The data is first loaded into the TX buffer. The MCU then requests that the MC13192/MC13193 transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted. In streaming mode, the data is fed to the MC13192/MC13193 on a word-by-word basis with an interrupt serving as a notification that the MC13192/MC13193 is ready for more data. This continues until the whole packet is transmitted.
Synch & Det
Correlator
LN A R F IN + R F IN -
1s t IF M ix er IF = 65 M Hz
2nd IF M ix er IF = 1 M Hz P M A
Dec im ation F ilter
B as eband M ix er
M atc hed F ilter P ac k et P roc es s or
A nalog R egulator P ow er-U p C ontrol Logic Digital R egulator L Digital R egulator H C ry s tal R egulator R ec eiv e P ac k et R A M R ec eiv e R A M A rbiter VC O R egulator
V DDA VBAT T V DDIN T
CCA
DC D
Symbol
V DDD
V DDV C O
AGC P rogram m able P res c aler S equenc e M anager (C ontrol Logic )
R XT XEN
V D D LO 2
256 M Hz
/4
24 B it E v ent T im er
SERIAL PERIPHERAL
INTERFACE (SPI)
4 P rogram m able T im er C om parators
CE M OSI M IS O S P IC LK AT T N R ST
X T A L1 X T A L2
C ry s tal O s c illator
16 M Hz
S y nth esize r
T rans m it P ac k et R A M 2
T rans m it P ac k et R A M 1 V DDLO 1 2.45 G Hz V CO T rans m it R A M A rbiter S y m bol G eneration IR Q A rbiter
G P IO 1 G P IO 2 G P IO 3 G P IO 4 G P IO 5 G P IO 6 G P IO 7 IR Q
PAO+ PAO-
PA
P has e S hift M odulator
MUX
C LK O
FCS G eneration
Header G eneration
Figure 3. MC13192 Simplified Block Diagram
MC13192/MC13193 Technical Data, Rev. 2.9 6 Freescale Semiconductor
Data Transfer Modes
MC13192/MC13193 Analog Receiver Digital Transceiver Control Logic SPI and GPIO
Microcontroller SPI Timer A/D ROM (Flash) RAM RAM Arbiter IRQ Arbiter Timer CPU Application Network
Frequency Generation
Analog Transmitter
Voltage Regulators
Power Up Management
Buffer RAM
MAC PHY Driver
Figure 4. System Level Block Diagram
4 bytes Preamble
1 byte SFD
1 byte FLI
125 bytes maximum Payload Data
2 bytes FCS
Figure 5. MC13192/MC13193 Packet Structure
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 7
Electrical Characteristics
5
5.1
Electrical Characteristics
Maximum Ratings
Table 1. Absolute Maximum Ratings
Rating Power Supply Voltage RF Input Power Junction Temperature Storage Temperature Range Symbol VBATT, VDDINT Pmax TJ Tstg Value 3.6 10 125 -55 to 125 Unit Vdc dBm C C
Note: Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables. Note: Meets Human Body Model (HBM) = 2 kV and Machine Model (MM) = 200 V except RFIN = 100 V MM, PAO = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF output pins have no ESD protection.
5.2
Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Characteristic Symbol VBATT, VDDINT fin TA VIL VIH fSPI Pmax fref Min 2.0 2.405 -40 0 70% VDDINT Typ 2.7 25 Max 3.4 2.480 85 30% VDDINT VDDINT 8.0 10 Unit Vdc GHz C V V MHz dBm
Power Supply Voltage (VBATT = VDDINT) Input Frequency Ambient Temperature Range Logic Input Voltage Low Logic Input Voltage High SPI Clock Rate RF Input Power Crystal Reference Oscillator Frequency (40 ppm over operating conditions to meet the 802.15.4 standard.)
16 MHz Only
MC13192/MC13193 Technical Data, Rev. 2.9 8 Freescale Semiconductor
Electrical Characteristics
5.3
DC Electrical Characteristics
Table 3. DC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 C, unless otherwise noted) Characteristic Symbol Min Typ Max Unit
Power Supply Current (VBATT + VDDINT) Off Hibernate Doze (No CLKO) Idle Transmit Mode (0 dBm nominal output power) Receive Mode Input Current (VIN = 0 V or VDDINT) (All digital inputs) Input Low Voltage (All digital inputs)
Ileakage ICCH ICCD ICCI ICCT ICCR IIN VIL
0
0.2 1.0 35 500 30 37 -
1.0 6.0 102 800 35 42 1 30% VDDINT VDDINT VDDINT 20% VDDINT
A A A A mA mA A V
Input High Voltage (all digital inputs) Output High Voltage (IOH = -1 mA) (All digital outputs) Output Low Voltage (IOL = 1 mA) (All digital outputs)
VIH VOH VOL
70% VDDINT 80% VDDINT 0
-
V V V
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 9
Electrical Characteristics
5.4
AC Electrical Characteristics
NOTE All AC parameters measured with SPI Registers at default settings except where noted and the following registers over-programmed: Register 08 = 0xFFF7 and Register 11 = 0x20FF
Table 4. Receiver AC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 C, fref = 16 MHz, unless otherwise noted. Parameters measured at connector J6 of evaluation circuit.) Characteristic Symbol SENSper Min SENSmax Typ -92 -92 10 25 31 42 41 49 Max -87 200 80 Unit dBm dBm dBm dB dB dB dB dB kHz ppm
Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 C) Sensitivity for 1% Packet Error Rate (PER) (+25 C) Saturation (maximum input level) Channel Rejection for 1% PER (desired signal -82 dBm) +5 MHz (adjacent channel) -5 MHz (adjacent channel) +10 MHz (alternate channel) -10 MHz (alternate channel) >= 15 MHz Frequency Error Tolerance Symbol Rate Error Tolerance
Table 5. Transmitter AC Electrical Characteristics
(VBATT, VDDINT = 2.7 V, TA = 25 C, fref = 16 MHz, unless otherwise noted. Parameters measured at connector J5 of evaluation circuit.) Characteristic Power Spectral Density (-40 to +85 C) Absolute limit Power Spectral Density (-40 to +85 C) Relative limit Nominal Output Power1 Maximum Output Power2 Error Vector Magnitude Output Power Control Range (-27 dBm to +4 dBm typical) Over the Air Data Rate 2nd Harmonic 3rd Harmonic
1 2
Symbol
Min -
Typ -47 47 0 4
Max 3
Unit dBm
Pout
-3
dBm dBm
EVM
-
20 31 250 -42 -44
35 -
% dB kbps dBc dBc
SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical). SPI Register 12 programmed to 0x00FC which sets output power to maximum.
MC13192/MC13193 Technical Data, Rev. 2.9 10 Freescale Semiconductor
Electrical Characteristics
J5 SMA 2
J6 SMA 2 Y1 TSX-10A@16Mhz
1
1
C4 9pF 1 5 1 5
C5 9pF
2450BL15B200 3 2 4
T1 2450BL15B200 3 2 4
T2
+ C7 10pF C8 10pF
C1 220pF
+
C2 220pF C6 0.1uF 32 31 30 29 28 27 26 25 VDDA VBATT VDDVCO VDDLO1 VDDLO2 XTAL2 XTAL1 GPIO7 U1
L2
6.8nH 1 2 3 4 5 6 7 8
J1 R1 47k GPIO6 GPIO5 VDDINT VDDD IRQ CE MISO MOSI 24 23 22 21 20 19 18 17 + C3 220pF Baud SEL RTXENi RTXENi R4 47k MOSI CE VCC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 MCU Interface
R2 200 RFINRFIN+ GND GND PAO+ PAOGND GPIO4
J3 PA2 RXD GPIO2 1 2 Wake Up J4 16 MHz CLK 2 1 CLOCK Sel
L1
8.2nH
GPIO1 R3 10k IRQ
9 10 11 12 13 14 15 16
GPIO3 GPIO2 GPIO1 RST RXTXEN ATTN CLKO SPICLK
MC13192
MCU RESET ATTN SPI_CLK MISO
J7 1 2 3 RESET
GPIO2 GPIO1
ABEL RESET CLKO
R6 47k 1 3 5 7 9 11 13 15 17 19
R5 47k
J2 HEADER 10X2 2 4 6 8 10 12 14 16 18 20
Figure 6. Parameter Evaluation Circuit
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 11
Functional Description
6
6.1
Functional Description
MC13192/MC13193 Operational Modes
The MC13192/MC13193 has a number of operational modes that allow for low-current operation. Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 6. Current drain in the various modes is listed in Table 3, DC Electrical Characteristics.
Table 6. MC13192/MC13193 Mode Definitions and Transition Times
Mode Off Hibernate Doze Definition All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including IRQ Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained. Transition Time To or From Idle 25 ms to Idle 20 ms to Idle
Crystal Reference Oscillator On but CLKO output available only if Register (300 + 1/CLKO) s 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to Idle to ATTN and can be programmed to enter Idle Mode through an internal timer comparator. Crystal Reference Oscillator On with CLKO output available. SPI active. Crystal Reference Oscillator On. Receiver On. Crystal Reference Oscillator On. Transmitter On. 144 s from Idle 144 s from Idle
Idle Receive Transmit
6.2
Serial Peripheral Interface (SPI)
The host microcontroller directs the MC13192/MC13193, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13192/MC13193 occurs as multiple 8-bit bursts on the SPI. The SPI signals are: 1. Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts. 2. SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13192/MC13193. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK. NOTE For Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0. 3. Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input. 4. Master In/Slave Out (MISO) - The MC13192/MC13193 presents data to the master on the MISO output.
MC13192/MC13193 Technical Data, Rev. 2.9 12 Freescale Semiconductor
Functional Description
A typical interconnection to a microcontroller is shown in Figure 7.
MCU MC13192/MC13193
Shift Register
RxD TxD Sclk
MISO MOSI SPICLK Shift Register
Baud Rate Generator
Chip Enable (CE)
CE
Figure 7. SPI Interface
Although the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLKcore), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory.
6.2.1
SPI Burst Operation
The SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13192/MC13193 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure 8.
SPI Burst
CE 1 SPICLK T4 T6 T5 T7 MISO MOSI Valid Valid
Figure 8. SPI Single Burst Timing Diagram
2
3
4
5
6
7
8
Valid T3
T2 T1 T0
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 13
Functional Description
Table 7. SPI Timing Specifications
Symbol T0 T1 T2 T3 T4 T5 T6 T7 SPICLK period Pulse width, SPICLK low Pulse width, SPICLK high Delay time, MISO data valid from falling SPICLK Setup time, CE low to rising SPICLK Delay time, MISO valid from CE low Setup time, MOSI valid to rising SPICLK Hold time, MOSI valid from rising SPICLK Parameter Min 125 62.5 62.5 15 15 15 15 15 Typ Max Unit nS nS nS nS nS nS nS nS
6.2.2
SPI Transaction Operation
Although the SPI port of an MCU transfers data in bursts of 8 bits, the MC13192/MC13193 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to the MC13192/MC13193 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid). Although the SPI bus is capable of sending data simultaneously between master and slave, the MC13192/MC13193 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13192/MC13193 Reference Manual, part number MC13192RM for more details on SPI registers and transaction types. An example SPI read transaction with a 2-byte payload is shown in Figure 9.
CE Clock Burst SPICLK
MISO
Valid
Valid
MOSI
Valid Header Read data
Figure 9. SPI Read Transaction Diagram
MC13192/MC13193 Technical Data, Rev. 2.9 14 Freescale Semiconductor
Pin Connections
7
Pin # 1 2 3 4 5 6 7 8 9 10
Pin Connections
Table 8. Pin Function Description
Pin Name RFINRFIN+ Not Used Not Used PAO+ PAOSM GPIO41 GPIO31 GPIO21 RF Output /DC Input Type RF Input RF Input Description LNA negative differential input. LNA positive differential input. Tie to Ground. Tie to Ground. Power Amplifier Positive Output. Open drain. Connect to VDDA. Functionality
RF Output/DC Input Power Amplifier Negative Output. Open drain. Connect to VDDA. Test mode pin. Tie to Ground Digital Input/ Output General Purpose Input/Output 4. Digital Input/ Output General Purpose Input/Output 3. Digital Input/ Output General Purpose Input/Output 2. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO2 functions as a "CRC Valid" indicator. Digital Input/ Output General Purpose Input/Output 1. When gpio_alt_en, Register 9, Bit 7 = 1, GPIO1 functions as an "Out of Idle" indicator. Digital Input Active Low Reset. While held low, the IC is in Off Mode and all internal information is lost from RAM and SPI registers. When high, IC goes to IDLE Mode, with SPI in default state. Active High. Low to high transition initiates RX or TX sequence depending on SPI setting. Should be taken high after SPI programming to start RX or TX sequence and should be held high through the sequence. After sequence is complete, return RXTXEN to low. When held low, forces Idle Mode. Active Low Attention. Transitions IC from either Hibernate or Doze Modes to Idle. Clock output to host MCU. Programmable frequencies of: 16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5 kHz, 32.786+ kHz (default), and 16.393+ kHz. External clock input for the SPI interface. Tie to Ground for normal operation See Footnote 1 See Footnote 1 See Footnote 1
11
GPIO11
See Footnote 1
12
RST
13
RXTXEN
Digital Input
14 15
ATTN CLKO
Digital Input Digital Output
16
SPICLK
Digital Clock Input
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 15
Pin Connections
Table 8. Pin Function Description (continued)
Pin # 17 18 19 20 Pin Name MOSI MISO CE IRQ Type Digital Input Digital Output Digital Input Digital Output Description Master Out/Slave In. Dedicated SPI data input. Master In/Slave Out. Dedicated SPI data output. Active Low Chip Enable. Enables SPI transfers. Active Low Interrupt Request. Open drain device. Programmable 40 k internal pull-up. Interrupt can be serviced every 6 s with <20 pF load. Optional external pull-up must be >4 k. Decouple to ground. 2.0 to 3.4 V. Decouple to ground. See Footnote 1 See Footnote 1 See Footnote 1 Connect to 16 MHz crystal and load capacitor. Functionality
21 22 23 24 25 26 27
VDDD VDDINT GPIO51 GPIO61 GPIO71 XTAL1 XTAL2
Power Output Power Input
Digital regulated supply bypass. Digital interface supply & digital regulator input. Connect to Battery.
Digital Input/Output General Purpose Input/Output 5. Digital Input/Output General Purpose Input/Output 6. Digital Input/Output General Purpose Input/Output 7. Input Input/Output Crystal Reference oscillator input.
Crystal Reference oscillator output Connect to 16 MHz crystal and Note: Do not load this pin by using it as a 16 load capacitor. MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13192/MC13193 Reference Manual for details. LO2 VDD supply. Connect to VDDA externally. LO1 VDD supply. Connect to VDDA externally. VCO regulated supply bypass. Decouple to ground.
28 29 30 31 32
VDDLO2 VDDLO1 VDDVCO VBATT VDDA
Power Input Power Input Power Output Power Input Power Output
Analog voltage regulators Input. Connect to Decouple to ground. Battery. Analog regulated supply Output. Connect to Decouple to ground. directly VDDLO1 and VDDLO2 externally and to PAO through a frequency trap. Note: Do not use this pin to supply circuitry external to the chip. External paddle / flag ground. Connect to ground.
EP
1
Ground
The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state.
MC13192/MC13193 Technical Data, Rev. 2.9 16 Freescale Semiconductor
Pin Connections
32 VDDA
31 VBATT
30 VDDVCO
29 VDDLO1
28 VDDLO2
27 XTAL2
26 XTAL1
25 GPIO7
1 2 3 4 5 6 7 8
RFINRFIN+ NC NC
GPIO6 GPIO5
24 23 22 21 20 19 18 17
VDDINT VDDD EP
PAO+ PAOSM GPIO3 GPIO4 GPIO2
MC13192/ MC13193
RXTXEN GPIO1 SPICLK 16 RST ATTN CLKO
IRQ CE MISO MOSI
9
10
11
12
13
14
15
Figure 10. Pin Connections (Top View)
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 17
Applications Information
8
8.1
Applications Information
Crystal Oscillator Reference Frequency
The IEEE 802.15.4 Standard requires that several frequency tolerances be kept within 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13192/MC13193 transceiver provides onboard crystal trim capacitors to assist in meeting this performance. The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them: 1. The initial (or make) tolerance of the crystal resonant frequency itself. 2. The variation of the crystal resonant frequency with temperature. 3. The variation of the crystal resonant frequency with time, also commonly known as aging. 4. The variation of the crystal resonant frequency with load capacitance, also commonly known as pulling. This is affected by: a) The external load capacitor values - initial tolerance and variation with temperature. b) The internal trim capacitor values - initial tolerance and variation with temperature. c) Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray package capacitance and stray board capacitance; and its initial tolerance and variation with temperature. Freescale has specified that a 16 MHz crystal with a <9 pF load capacitance is required. The MC13192/MC13193 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13192/MC13193 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading. In the reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps. Initial tolerance for the internal trim capacitance is approximately 15%. Since the MC13192/MC13193 contains an on-chip reference frequency trim capability, it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on a board-by-board basis.
MC13192/MC13193 Technical Data, Rev. 2.9 18 Freescale Semiconductor
Applications Information
A tolerance analysis budget may be created using all the previously stated factors. It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging factor is usually specified in ppm/year and the product designer can determine how many years are to be assumed for the product lifetime. Taking all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the IEEE 802.15.4 specification.
8.2
Design Example
Figure 11 shows a basic application schematic for interfacing the MC13192/MC13193 with an MCU. Table 9 lists the Bill of Materials (BOM). The MC13192/MC13193 has differential RF inputs and outputs that are well suited to balanced printed wire antenna structures. Alternatively, as in the application circuit, a printed wire antenna, a chip antenna, or other single-ended structures can be used with commercially available chip baluns or microstrip equivalents. PAO+ and PAO- require a DC connection to VDDA (the analog regulator output) through AC blocking elements. This is accomplished through the baluns in the referenced design. The 16 MHz crystal should be mounted close to the MC13192/MC13193 because the crystal trim default assumes that the listed KDS Daishinku crystal (see Table 10) and the 6.8 pF load capacitors shown are used. If a different crystal is used, it should have a specified load capacitance (stray capacitance, etc.) of 9 pF or less. A second crystal that has been evaluated and also gives acceptable performance is the Toyocom TSX-10A 16 MHZ TN4-26139 (see Table 11). VDDA is an analog regulator output used to supply only the onboard PA (PAO+ and PAO-) and VDDLO1 and VDDLO2 pins. VDDA should not be used to power devices external to the transceiver chip. Bypassing capacitors are critical and should be placed close to the device. Unused pins should be grounded as shown. The SPI connections to the MCU include CE, MOSI, MISO, and SPICLK. The SPI can run at a frequency of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is programmable via the SPI and has a default of 32.786+ kHz (16 MHz / 488). The ATTN line can be driven by a GPIO from the MCU (as shown) or can also be controlled by a switch or other hardware. The latter approach allows the MCU to be put into a sleep mode and then awakened by CLKO when the ATTN line wakes up the MC13192/MC13193. RXTXEN is used to initiate receive, transmit or CCA/ED sequences under MCU control. RXTXEN must be controlled by an MCU GPIO with the connection shown. Device reset (RST) is controlled through a connection to an MCU GPIO. When the MC13192/MC13193 is used in Stream Mode, as with 802.15.4 MAC/PHY software, the MC13192/MC13193 GPIO1 functions as an "Out of Idle" indicator and GPIO2 functions as a "CRC Valid" / Clear Channel Assessment (CCA) result indicator and are not available for general purpose use.
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 19
Applications Information
32 29 28 21 30 C5 6.8pF XTAL1 26 X1 VDDA VDDLO1 VDDLO2 VDDD VDDVCO
1 2 3 4 5 J1 SMA Receptacle, Female
20
IC1 RIN_M Z1 4 L1 6.8nH 3 RIN_P C9 10pF C7 10pF Not Used IRQB IC2 6 C11 5 4 PG 2012TK-E2 VDDA 4 2 3 PAO_M 3V0_RF 31 22 VBATT VDDINT Not Used 7 VDDA C8 10pF 50_Ohm7 6 100_Ohm4 LDB212G4020C-001 1 50_Ohm2 5 6 L2 8.2nH 15 CLKO Z2 C10 10pF 10pF L3 8.2nH C12 0.5pF R3 0 ANT1 F_Antenna 50_Ohm6 R2 0 Not Used 2 14 13 12 ATTNB RXTXEN RSTB PAO_P 5 100_Ohm3 4 50_Ohm3 3 50_Ohm4 1 OUT2 VDD OUT1 IN GND VCONT 3 CEB MISO MOSI SPICLK 2 100_Ohm2 LDB212G4020C-001 1 50_Ohm1 2 5 6 11 10 9 8 23 24 25 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 19 18 17 16 20 3V0_BB R1 470K 1 100_Ohm1 C1 1F GND 16.000MHz C6 6.8pF MC13192 XTAL2 27 C2 220nF C3 220nF C4 220nF EP
SS MISO MOSI SCLK
IRQ
GPIO GPIO GPIO GPIO GPIO GPIO
CLK
Figure 11. MC13192/MC13193 Configured With a MCU
MC13192/MC13193 Technical Data, Rev. 2.9
MCU
Freescale Semiconductor
Applications Information
Table 9. MC13192/MC13193 to MCU Bill of Materials (BOM)
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Quantity 1 1 3 2 5 1 1 1 1 1 2 1 2 1 2 Reference ANT1 C1 C2, C3, C4 C5, C6 C7, C8, C9, C10, C11 C12 IC1 IC2 J1 L1 L2, L3 R1 R2, R3 X1 Z1, Z2 Part F_Antenna 1 F 220 nF 6.8 pF 10 pF 0.5 pF MC13192/MC13193 PG2012TK-E2 SMA Receptacle, Female 6.8 nH 8.2 nH 470 k 0 16.000 MHz, Type DSX321G, ZD00882 LDB212G4020C-001 KDS, Daishinku Corp Murata Freescale Semiconductor NEC Manufacturer Printed wire
Table 10. Daishinku KDS - DSX321G ZD00882 Crystal Specifications
Parameter Type Frequency Frequency tolerance Equivalent series resistance Temperature drift Load capacitance Drive level Shunt capacitance Mode of oscillation Value DSX321G 16 20 100 20 8.0 10 2 MHz ppm ppm pF W pF 2 W max fundamental at 25 C 3 C max -10 C to +60 C Unit Condition surface mount
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 21
Applications Information
Table 11. Toyocom TSX-10A 16MHZ TN4-26139 Crystal Specifications
Parameter Type Frequency Frequency tolerance Equivalent series resistance Temperature drift Load capacitance Drive level Shunt capacitance Mode of oscillation Value TSX-10A 16 10 40 16 9 100 1.2 MHz ppm ppm pF W pF max typical fundamental at 25 C 3 C max -40 C to +85 C Unit Condition surface mount
MC13192/MC13193 Technical Data, Rev. 2.9 22 Freescale Semiconductor
Packaging Information
9
Packaging Information
PIN 1 INDEX AREA 0.1 A 0.1 2X C G 1.0 0.8 5 (0.25) 0.05 0.00 (0.5) C DETAIL G VIEW ROTATED 90 CLOCKWISE M B 0.1 C 3.25 2.95 EXPOSED DIE ATTACH PAD 25 24 32 A B DETAIL M PIN 1 INDEX SEATING PLANE 1.00 0.75 0.05 C 5 5 2X M 0.1 C C
1 0.25
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND DIE ATTACH PAD. 6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12.
3.25 2.95 0.1 C A B 0.5 N 32X 0.30 0.18 0.1 VIEW M-M 0.05 M M C C DETAIL S PREFERRED BACKSIDE PIN 1 INDEX (45 5 ) DETAIL S A B (0.25) (0.1) 28X 0.217 0.137 17 16 32X 0.5 0.3 9 8 0.217 0.137
(1.73)
0.60 0.24
32X
0.065 0.015
(0.25) DETAIL N PREFERRED CORNER CONFIGURATION 4
0.60 0.24 DETAIL N CORNER CONFIGURATION OPTION 4 DETAIL M PREFERRED BACKSIDE PIN 1 INDEX
DETAIL T 0.475 0.425
1.6 1.5
5
BACKSIDE PIN 1 INDEX
(90 )
2X
0.39 0.31
R DETAIL M BACKSIDE PIN 1 INDEX OPTION
0.25 0.15 DETAIL M BACKSIDE PIN 1 INDEX OPTION DETAIL T BACKSIDE PIN 1 INDEX OPTION
2X
0.1 0.0
Figure 12. Outline Dimensions for QFN-32, 5x5 mm (Case 1311-03, Issue E)
MC13192/MC13193 Technical Data, Rev. 2.9 Freescale Semiconductor 23
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Document Number: MC13192 Rev. 2.9 08/2005

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